The present invention concerns a means for providing addressability in an apparatus comprising one or more volume elements, wherein said volume or volume elements together with said means form a part of a two- or three-dimensional matrix in said apparatus, wherein a volume element comprises one or more cells having a data storage, data-processing or signal-processing functionality depending on the electronic or electric properties of a material of said volume element, wherein said means provides addressability to a specific location in a volume element by establishing a selective electrical connection to said volume element or in case said volume element comprises more than one cell, a specific cell thereof, wherein the selection of a specific volume element or cell thereof takes place by a providing a not necessarily simultaneous electrical connection to three or more electrodes formed by said means and contacting said volume element for effecting a selective interaction therewith in a region thereof in close proximity to said electrodes, and wherein said region defines a cell in said volume element thus interacted upon.
The present invention also concerns an apparatus comprising such means wherein the means together with one or more volume elements form a part of a two- or three-dimensional matrix in said apparatus, wherein a volume element comprises one or more cells having a data storage, data-processing or signal-processing functionality depending on the electronic or electric properties of a material of said volume element, and wherein the apparatus comprises more than one matrix of this kind.
Generally the present invention discloses addressing architectures that provide electronic N-terminal access to volume elements or regions thereof in two- or three-dimensional matrix structures, where the number N of terminals to be connected at each address in the matrix is at least three.
Orthogonal addressing matrices in two dimensions are employed extensively in a wide variety of electronic devices such as cameras, memory devices and displays where it is required to have unique electronic access to each individual matrix element.
The simplest type of matrices consists of one set of mutually parallel electrode lines (termed xe2x80x9caxe2x80x9d electrodes below) in one plane, located in proximity to another parallel plane containing another set of mutually parallel electrode lines (termed xe2x80x9cbxe2x80x9d electrodes below). The xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d set of electrodes are oriented so as to cross each other, typically in orthogonal fashion, providing addressability to the volume elements between the crossing electrodes. Thus, the volume element between electrode ai in the xe2x80x9caxe2x80x9d electrode set and electrode bj in the xe2x80x9cbxe2x80x9d electrode set can be acted upon electrically by connecting the electrodes ai and bj to an appropriate source of current or voltage. The volume elements can accommodate active circuit elements capable of being triggered by an input signal, or in themselves be provided as switching or as passive elements, a physical state of which may be altered by applying an input signal or detected upon addressing in the xe2x80x9caxe2x80x9d and the xe2x80x9cbxe2x80x9d electrodes, then being capable of realizing memory elements for storing binary or multilevel logical values.
A device based on matrices of this kind are e.g. disclosed in International patent application No. PCT/NO98/00185 (U.S. Pat. No. 6,055,180), assigned to the present applicant. This concerns an electrically addressable passive device which can be used in optical detector means, volumetric data storage devices or data processing devices. The disclosed device comprises a functional medium in the form of a continuous or patterned structure which may undergo a physical or chemical change of state. This functional medium which corresponds to the volume element or the present invention, comprises individually addressable cells provided between the anode and cathode in an electrode means which contacts the functional medium in the cell and causes an electrical coupling thereto. The anodes are provided as a first set parallel stripe-like electrodes in a layer contacting the functional medium on one side and the cathodes are provided as a second set of stripe-like electrodes that contacts the functional medium on the other side, the stripe-like electrodes in each set being mutually parallel and each electrode set being oriented such that the electrodes therein in one are oriented orthogonal with respect to the electrodes in the other. In practice a cell in the volume element of the functional medium is now defined at the crossing of a stripe-like electrode of the first set with a stripe-like electrode of the second set. When a cell in this device is addressed, e.g. for writing, reading or switching of e.g. a logical value assigned to a cell, electric energy is applied directly to the functional medium of the cell via a selected pair of crossing electrodes in respectively the first and the second set.
International patent application No. PCT/NO98/00212, likewise assigned to the present applicant discloses, a similar device, wherein, however, the electrode matrix is provided with the electrode set mutually isolated in a bridge arrangement and the functional medium provided over and covering the electrode sets. In addition to its possible use as an electrical addressable memory device, this particular arrangement with bridged electrodes covered by the functional medium, as opposed to the above-mentioned device wherein the functional medium is provided in sandwich between the electrodes, facilitates its use in for instance in an optical or electronic camera or in a chemical camera or in an electrically addressable display device.
Finally International patent application PCT/NO98/00237, also assigned to the present applicant, discloses a ferroelectric device for processing and/or storage of data with passive electrical addressing of the functional medium which is a thin film of ferroelectric material provided over and covering the electrode sets which also here are provided in a bridged arrangement.
In all the above-mentioned devices the functional medium corresponding to a volume element provided between or over the electrode sets can be deposited as a global layer, in which the individual cells of course, always will be defined by the crossings between electrodes in the first and second electrode set respectively. However, the functional medium forming the element may also be patterned or pixelated such that individual volume elements is provided between or over the crossing of the electrodes in the respective sets, thereby forming a volume element comprising only one cell. This, of course, does not affect the total possible number of cells in the matrix, as this essentially will be the product of the number of electrodes in each set.
In arrays and matrices of the above-mentioned kind that store or process electrical signals the matrix or array elements thus defined may include various kind of components and circuitry, depending on the application, but at each crossing point only two independent electrical connections to the outside world is possible. Thus, the two sets of electrodes can only support exclusive addressing to two terminal devices or circuits, due to the two dimensions available.
Several approaches are used today in electronic systems based on matrices and where each matrix element requires more than two terminal connections. In SRAM technology the memory cells require more than two terminals, i.e. Vcc, bit, xe2x88x92bit and word. A prior art matrix solution for addressing the memory cells in SRAM technology is shown in FIG. 1 and uses two parallel lines, Vcc line and word line, oriented perpendicular to two other parallel lines, xe2x88x92bit and bit lines. No exclusive addressing can be obtained between the two parallel lines, i.e. no exclusive addressing between xe2x88x92bit and bit for instance.
Another prior art solution for realizing exclusive addressing between more than two lines (or electrodes) is shown in FIG. 2. Here a three-dimensional matrix is used. Exclusive addressing is now obtained between a certain set of lines ai, bj and ck. By only choosing the combination ai, bj a column is chosen and a specific element is not addressed until also ck is specified. Any element that fulfils the requirement ixcex5(1, imax), jxcex5(1, jmax) and kxcex5(1, kmax) can be reached through an addressing combination of ai, bj and ck.
The physical implementation of the addressing schemes discussed above is not simple when each element in the matrix shall be accessed by three or more terminals.
In two-dimensional prior art cases, as exemplified above for SRAM devices and shown in FIG. 1, electronic circuitry is typically made in quasi-planar fashion when the physical location of each element in the matrix is defined by two coordinates. Layer is built upon layer in a series of deposition, masking and etching steps involving precision alignment operations, etc. This approach affords only limited scalability and flexibility, and leads to rapidly increasing topological complexity as the number of terminals at each matrix coordinate increases.
Regarding true three-dimensional matrix addressing schemes as shown in FIG. 2, there are as far as can be ascertained no examples of high-density prior art devices made by mass manufacturing processes. In practice functional addressing schemes for matrix addressing in three-dimensions have not been easy to implement while simultaneously achieving low complexity and high compatibility with simple and cheap manufacturing processes.
Thus it is a major object of the present invention to obviate the above-mentioned disadvantages of the prior art by providing generic architectures for addressing N-terminal (N greater than 2) electronic devices or elements arranged physically in matrix fashion in two or three dimensions.
Another object of the present invention is to provide a simple and practical means for uniquely connecting a single N-terminal element in a two-dimensional matrix with n external voltage or current terminals, where 2xe2x89xa6nxe2x89xa6N.
The above-mentioned objects and other features and advantages are achieved according to the invention with a means which is characterized in that it comprises at least three sets of plural electrically conducting lines or strip-like electrodes, that each electrode set comprises said strip-like electrodes provided in a substantially parallel relationship to each other in a respective two-dimensional planar layer forming an additional part of said matrix, said layers of electrode sets being substantially mutually parallel, that a set of strip-like electrodes in one layer is oriented at an angle to the projected angle of orientation of the electrode sets of the proximal neighbouring layers on said one layer, such that said sets or strip-like electrodes in proximal neighbouring layers exhibit a mutual non-orthogonal relationship, and that said electrodes contacting a said region of a volume element are formed by a crossing of three or more of said strip-like electrodes in said respective electrode sets contacting said volume element, such that said cell or cells of said volume element in any case is located therein between or at said crossing of said three or more strip-like electrodes, a selective addressing of a cell taking place by applying a current or voltage to a selected strip-like electrode in each of the electrode sets either simultaneously or in a temporal sequence defined by a predetermined addressing protocol.
In an advantageous embodiment of the means according to the invention the substantially parallel strip-like electrodes are provided equidistantly spaced apart.
In another advantageous embodiment of the means according to the invention an electrode set in the matrix is provided rotated about an axis substantially perpendicular thereto, by a given angle or angles, in relation to at least the proximal neighbouring electrode sets, such that none of the strip-like electrodes in said proximal neighbouring electrode sets conformally overlap. Preferably are then all electrode sets in the matrix are provided mutually rotated about an axis substantially perpendicular thereto, by a given angle or angles such that none of the strip-like electrode in any other electrode sets conformally overlap, or alternatively is the given angle of rotation between an electrode set and a following proximal neighbouring electrode set 2xcfx80/mxc2x7N or 360xc2x0 mN, N being the number of the strip-like electrodes respectively contacting a terminal in a cell and m an integer such that mxe2x89xa6N.
In various advantageous embodiments of the means according to the invention the means comprises three electrode sets for providing an electrical connection to cells with up to three terminals, or four electrode sets for providing an electrical connection to cells with up to four terminals, or three electrode sets for providing an electrical connection to at least two cells with up to two terminals each.
According to the invention the number of strip-like electrodes provided in a respective electrode set is selected with regard to the number and geometrical arrangements of the cells in the matrix, so as to maximize the number of addressable cells therein, and preferably is then a number of strip-like electrodes provided in a respective electrode set is selected so as to enable the addressing of a cell in the matrix.
In an embodiment of the means according to the invention wherein each cell in a volume element in the matrix is provided with at least two terminals, it is considered advantageous providing the electrode layers and the layer or layers forming the volume element in a sandwich arrangement, an electrode adjoining a surface of at least one volume element layer in an interfacing relationship thereto, whereby the crossing between the strip-like electrodes in each electrode layer defines a cell in the volume element, and preferably is then a diode junction provided between an electrode in an electrode crossing and a cell defined thereby.
Finally, an embodiment of the means according to the invention wherein one or more cells in the volume element comprises at least one transistor structure at least one electrode in at least two electrode sets respectively contacts the terminals of said at least one transistor structures, and if more than one volume element comprises more than one transistor structure, then preferably at least one electrode in at least two electrode sets respectively connects the transistors electrically with each other via the terminals thereof.
The apparatus according to the present invention is characterized in that the matrices are provided in a stacked arrangement, whereby the apparatus forms a volumetric structure of stacked matrices for data storage, data processing, or a signal processing as given by the functionality of each matrix in the stack.
In an advantageous embodiment of the apparatus according to the invention the apparatus is provided on a substrate comprising integrated circuitry connected with the electrodes of the means for implementing driving control and error correcting functions in the cells of the volume elements of the matrices.